Signal averaging circuits and methods are used in a wide range of applications including, for example, processing motion-sensitive output from a array of photo-detectors in an optical navigation system.
One common application of a signal averaging circuit is to compute a running average, weighted or un-weighted, over a fixed number of samples. A conventional method for computing a running average over a predetermined number (N) of samples is schematically illustrated in FIG. 1. Referring to FIG. 1, a queue 100, such as one implemented using a first-in-first-out or FIFO register, of depth N is required for storing N samples. New or most recent sample values are loaded or pushed into a head of the queue, shown as address 0, while simultaneously old sample is popped out from a tail of the queue, shown as address N-1, and discarded. A sum of all entries in queue is computed at every update of queue. Once the queue is full, the running average can be computed at every time a new sample is received by dividing the sum of the values in the queue by N.
A block diagram of a conventional signal averaging circuit for computing a running average over N samples according to the above method is shown in FIG. 2. Referring to FIG. 2, the averaging circuit 200, includes a queue storage 202, such as a FIFO register, of depth N, for storing N samples, a sum storage 204 for storing a sum of values stored in the queue, an adder 206 for adding a new sample to the sum in the sum storage, a subtractor 208 for subtracting the old, discarded sample value to generate an updated sum, which is stored in sum storage and divided by N in a divider 210 to compute the running or rolling average over N samples. The averaging circuit 200 shown in FIG. 2 is accurate and relatively fast, since it is not necessary to sum all values stored in the queue 202 every time a new sample is received. However, the above circuit is not wholly satisfactory for a number of reasons.
In particular, the implementation of FIG. 2 requires a large number of transistors, often referred to as gate count, for implementation of the storage queue 202. For example, one use for an averaging circuit, i.e., estimating average speed of the motion from an array of photo-detectors in an optical navigation system, typically requires a storage queue capable of storing about 64 samples, i.e., N=64, and has a gate count of from about 10 thousand to about 100 thousand gates. Because the averaging circuit is typically fabricated as an application specific integrated circuit (ASIC) along with the photo-detector array and a signal processor, this can account for as much as 10% of the IC or chip space, and significantly impact the power consumption of the optical navigation system in which it is included. This is especially of concern in battery operated devices, such as a wireless optical mouse.
Yet another problem with conventional averaging methods and circuits is an inability to vary the length or number of samples, N, over which the running average is computed. That is once the ASIC has been designed and fabricated for a specific value of N, it cannot be changed, rather a new ASIC must be designed and fabricated. Moreover, because the size of the storage queue increases linearly with N there are practical limits on the number of samples over which the running average can be computed.
Accordingly, there is a need for averaging circuit and method to compute a running average over a number of samples that eliminates the need for maintaining large queues or queuing registers. It is further desirable that the circuit and method enables adjustment of the averaging length (N) without significant impact if any on design of an ASIC in which the averaging circuit is included.
The present invention provides a solution to this and other problems, and offers further advantages over conventional signal averaging circuits and methods.